The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device with a structure suited to attain a high integration density or high performance, and a method of fabricating the semiconductor integrated circuit device.
Recently, the fabrication of a semiconductor large scale integration circuit device has been restricted by the interconnection technology for connecting diffusion regions having different conductivity types to each other and for connecting gate electrodes having different conductivity types to each other. Let us consider an integrated circuit having CMOS memory cells, by way of example. In order to make the memory cell small in size, it is necessary to connect the P.sup.+ -type source/drain region of a PMOSFET, the N.sup.+ -type source/drain region of NMOSFET, and the gate electrodes of the PMOSFET and the NMOSFET to each other. According to a conventional method, a wiring conductive layer is connected between the source/drain regions or gate electrodes through contact holes. In this case, the memory cell is obliged to be large in area, and thus it is impossible to improve the integration density or performance of the integrated circuit device. Further, in a case where a gate electrode is directly connected to a diffusion layer such as a source/drain region, there arises the following problem. The gate electrode is usually formed of a highly-doped, N-type, polycrystalline silicon layer (namely, N.sup.+ -polysilicon layer) and a metal silicide layer which is made of the silicide of a metal having a high melting point, (for example, tungsten silicide WSi.sub.2 layer). When the gate electrode is directly connected to the source/drain region of a PMOSFET (namely, P.sup.+ -region), the dopant contained in the n.sup.+ -polysilicon layer (for example, phosphorus) diffuses into the boundary between the N.sup.+ -polysilicon layer and the P.sup.+ -region. Hence, it is impossible to put the gate electrode in ohmic contact with the source/drain region, or the gate electrode may be shorted to the N-well region of the PMOSFET. Thus, the memory cell cannot perform the function thereof.
In order to solve the above problem, a method of connecting the gate electrode to the source/drain region has been proposed. According to this method, as described in a Japanese patent application JP-A-62-257749, a plurality of MOSFET's (that is, MOS transistors) are formed on a semiconductor substrate, and the source/drain region of each MOS transistor and the surface of each gate electrode made of polysilicon are exposed. Further, titanium is deposited on the surface, and the structure thus obtained is heated in an atmosphere of nitrogen to form titanium nitride and titanium silicide (TiN/TiSi.sub.2) on a surface area where silicon is exposed, and to form titanium nitride (TiN) on an oxide film in a self-alignment manner. Thereafter, the TiN layer is selectively etched to form a desired pattern. Thus, the TiN layer can be kept in contact with the surfaces of the gate electrode and the source/drain region. According to the above method, the TiN layer acts as the conductive diffusion barrier for a dopant. Hence, the TiN layer having a relatively small area can be put in ohmic contact with each of the gate electrode and source/drain region which are opposite in conductivity type to each other. In the above method, however, the TiN layer serving as a connecting conductor is etched so as to be put in contact with each of the gate electrode and the source/drain region. When the mask alignment accuracy in photolithograph and other factors are taken into consideration, it is necessary to make an area where the TiN layer is to be put in contact with each of the gate electrode and the source/drain electrode, sufficiently large. Accordingly, the improvement in integration density and performance of a semiconductor integrated circuit device is limited.
Further, an LDD (light-doped drain) MOSFET has been proposed to form a semiconductor integrated circuit device having a high integration density. An example of the LLDMOSFET is described on pages 38 to 41 of the IEDM 87. It has been earnestly desired to develop a structure capable of miniaturizing the LDDMOSFET and a method of fabricating the structure.